}
}
+
+void hvm_stts(struct vcpu *v)
+{
+ /* FPU state already dirty? Then no need to setup_fpu() lazily. */
+ if ( test_bit(_VCPUF_fpu_dirtied, &v->vcpu_flags) )
+ return;
+
+ hvm_funcs.stts(v);
+}
+
+void hvm_set_guest_time(struct vcpu *v, u64 gtime)
+{
+ u64 host_tsc;
+
+ rdtscll(host_tsc);
+
+ v->arch.hvm_vcpu.cache_tsc_offset = gtime - host_tsc;
+ hvm_funcs.set_tsc_offset(v, v->arch.hvm_vcpu.cache_tsc_offset);
+}
+
+void hvm_do_resume(struct vcpu *v)
+{
+ ioreq_t *p;
+ struct periodic_time *pt =
+ &v->domain->arch.hvm_domain.pl_time.periodic_tm;
+
+ hvm_stts(v);
+
+ /* pick up the elapsed PIT ticks and re-enable pit_timer */
+ if ( pt->enabled && pt->first_injected ) {
+ if ( v->arch.hvm_vcpu.guest_time ) {
+ hvm_set_guest_time(v, v->arch.hvm_vcpu.guest_time);
+ v->arch.hvm_vcpu.guest_time = 0;
+ }
+ pickup_deactive_ticks(pt);
+ }
+
+ p = &get_vio(v->domain, v->vcpu_id)->vp_ioreq;
+ wait_on_xen_event_channel(v->arch.hvm.xen_port,
+ p->state != STATE_IOREQ_READY &&
+ p->state != STATE_IOREQ_INPROCESS);
+ if ( p->state == STATE_IORESP_READY )
+ hvm_io_assist(v);
+ if ( p->state != STATE_INVALID ) {
+ printf("Weird HVM iorequest state %d.\n", p->state);
+ domain_crash(v->domain);
+ }
+}
+
void hvm_release_assist_channel(struct vcpu *v)
{
free_xen_event_channel(v, v->arch.hvm_vcpu.xen_port);
/*
* Copy from/to guest virtual.
*/
-int
-hvm_copy(void *buf, unsigned long vaddr, int size, int dir)
+int hvm_copy(void *buf, unsigned long vaddr, int size, int dir)
{
unsigned long mfn;
char *addr;
register_portio_handler(PIT_BASE, 4, handle_pit_io);
/* register the speaker port */
register_portio_handler(0x61, 1, handle_speaker_io);
- ticks_per_sec(v) = cpu_khz * (int64_t)1000;
+ ticks_per_sec(v) = cpu_khz * (int64_t)1000;
#ifdef DEBUG_PIT
printk("HVM_PIT: guest frequency =%lld\n", (long long)ticks_per_sec(v));
#endif
s->pics[1].elcr_mask = 0xde;
s->irq_request = irq_request;
s->irq_request_opaque = irq_request_opaque;
- return;
}
void pic_set_alt_irq_func(struct hvm_virpic *s,
}
void register_pic_io_hook (void)
{
- register_portio_handler(0x20, 2, intercept_pic_io);
- register_portio_handler(0x4d0, 1, intercept_elcr_io);
- register_portio_handler(0xa0, 2, intercept_pic_io);
- register_portio_handler(0x4d1, 1, intercept_elcr_io);
+ register_portio_handler(0x20, 2, intercept_pic_io);
+ register_portio_handler(0x4d0, 1, intercept_elcr_io);
+ register_portio_handler(0xa0, 2, intercept_pic_io);
+ register_portio_handler(0x4d1, 1, intercept_elcr_io);
}
}
}
+void hvm_interrupt_post(struct vcpu *v, int vector, int type)
+{
+ struct periodic_time *pt =
+ &(v->domain->arch.hvm_domain.pl_time.periodic_tm);
+
+ if ( is_pit_irq(v, vector, type) ) {
+ if ( !pt->first_injected ) {
+ pt->pending_intr_nr = 0;
+ pt->last_plt_gtime = hvm_get_guest_time(v);
+ pt->scheduled = NOW() + pt->period;
+ set_timer(&pt->timer, pt->scheduled);
+ pt->first_injected = 1;
+ } else {
+ pt->pending_intr_nr--;
+ pt->last_plt_gtime += pt->period_cycles;
+ hvm_set_guest_time(v, pt->last_plt_gtime);
+ pit_time_fired(v, pt->priv);
+ }
+ }
+
+ switch(type) {
+ case APIC_DM_EXTINT:
+ break;
+
+ default:
+ vlapic_post_injection(v, vector, type);
+ break;
+ }
+}
+
+
void hvm_io_assist(struct vcpu *v)
{
vcpu_iodata_t *vio;
case 0x4:
value = (unsigned long)vmcb->rsp;
case 0x5:
- value = regs->ebp;
+ value = regs->ebp;
break;
case 0x6:
value = regs->esi;
enum instruction_index *list, unsigned int list_count,
u8 *guest_eip_buf, enum instruction_index *match)
{
- unsigned int inst_len = 0;
+ unsigned int inst_len = 0;
unsigned int i;
unsigned int j;
int found = 0;
* Most of this code is copied from vmx_io.c and modified
* to be suitable for SVM.
*/
-#define BSP_CPU(v) (!(v->vcpu_id))
-
-void svm_set_guest_time(struct vcpu *v, u64 gtime)
-{
- u64 host_tsc;
-
- rdtscll(host_tsc);
-
- v->arch.hvm_vcpu.cache_tsc_offset = gtime - host_tsc;
- v->arch.hvm_svm.vmcb->tsc_offset = v->arch.hvm_vcpu.cache_tsc_offset;
-}
-
-static inline void
-interrupt_post_injection(struct vcpu * v, int vector, int type)
-{
- struct periodic_time *pt = &(v->domain->arch.hvm_domain.pl_time.periodic_tm);
-
- if ( is_pit_irq(v, vector, type) ) {
- if ( !pt->first_injected ) {
- pt->pending_intr_nr = 0;
- pt->last_plt_gtime = hvm_get_guest_time(v);
- pt->scheduled = NOW() + pt->period;
- set_timer(&pt->timer, pt->scheduled);
- pt->first_injected = 1;
- } else {
- pt->pending_intr_nr--;
- pt->last_plt_gtime += pt->period_cycles;
- svm_set_guest_time(v, pt->last_plt_gtime);
- pit_time_fired(v, pt->priv);
- }
- }
-
- switch(type)
- {
- case APIC_DM_EXTINT:
- break;
-
- default:
- vlapic_post_injection(v, vector, type);
- break;
- }
-}
static inline int svm_inject_extint(struct vcpu *v, int trap, int error_code)
{
{
struct vcpu *v = current;
struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
- struct hvm_domain *plat=&v->domain->arch.hvm_domain;
+ struct hvm_domain *plat=&v->domain->arch.hvm_domain;
struct periodic_time *pt = &plat->pl_time.periodic_tm;
struct hvm_virpic *pic= &plat->vpic;
int callback_irq;
/* let's inject this interrupt */
TRACE_3D(TRC_VMX_INT, v->domain->domain_id, intr_vector, 0);
svm_inject_extint(v, intr_vector, VMX_DELIVER_NO_ERROR_CODE);
- interrupt_post_injection(v, intr_vector, intr_type);
+ hvm_interrupt_post(v, intr_vector, intr_type);
break;
case APIC_DM_SMI:
case APIC_DM_NMI:
#define set_segment_register(name, value) \
__asm__ __volatile__ ( "movw %%ax ,%%" STR(name) "" : : "a" (value) )
-/*
- * External functions, etc. We should move these to some suitable header file(s) */
+/* External functions. We should move these to some suitable header file(s) */
extern void do_nmi(struct cpu_user_regs *, unsigned long);
extern int inst_copy_from_guest(unsigned char *buf, unsigned long guest_eip,
static int svm_do_vmmcall_reset_to_realmode(struct vcpu *v,
struct cpu_user_regs *regs);
+/* va of hardware host save area */
+static void *hsa[NR_CPUS] __read_mostly;
+/* vmcb used for extended host state */
+static void *root_vmcb[NR_CPUS] __read_mostly;
-extern void set_hsa_to_guest( struct arch_svm_struct *arch_svm );
+/* physical address of above for host VMSAVE/VMLOAD */
+u64 root_vmcb_pa[NR_CPUS] __read_mostly;
+
+
+/* ASID API */
+enum {
+ ASID_AVAILABLE = 0,
+ ASID_INUSE,
+ ASID_RETIRED
+};
+#define INITIAL_ASID 0
+#define ASID_MAX 64
+
+struct asid_pool {
+ spinlock_t asid_lock;
+ u32 asid[ASID_MAX];
+};
+
+static DEFINE_PER_CPU(struct asid_pool, asid_pool);
-/* Host save area and ASID glogal data */
-struct svm_percore_globals svm_globals[NR_CPUS];
/*
* Initializes the POOL of ASID used by the guests per core.
{
int i;
- spin_lock_init(&svm_globals[core].ASIDpool.asid_lock);
+ spin_lock_init(&per_cpu(asid_pool,core).asid_lock);
/* Host ASID is always in use */
- svm_globals[core].ASIDpool.asid[INITIAL_ASID] = ASID_INUSE;
+ per_cpu(asid_pool,core).asid[INITIAL_ASID] = ASID_INUSE;
for ( i = 1; i < ASID_MAX; i++ )
- svm_globals[core].ASIDpool.asid[i] = ASID_AVAILABLE;
+ per_cpu(asid_pool,core).asid[i] = ASID_AVAILABLE;
}
/* internal function to get the next available ASID */
static int asidpool_fetch_next(struct vmcb_struct *vmcb, int core)
{
- int i;
+ int i;
for ( i = 1; i < ASID_MAX; i++ )
{
- if ( svm_globals[core].ASIDpool.asid[i] == ASID_AVAILABLE )
+ if ( per_cpu(asid_pool,core).asid[i] == ASID_AVAILABLE )
{
vmcb->guest_asid = i;
- svm_globals[core].ASIDpool.asid[i] = ASID_INUSE;
+ per_cpu(asid_pool,core).asid[i] = ASID_INUSE;
return i;
}
}
int asidpool_assign_next( struct vmcb_struct *vmcb, int retire_current,
int oldcore, int newcore )
{
- int i;
+ int i;
int res = 1;
static unsigned long cnt=0;
- spin_lock(&svm_globals[oldcore].ASIDpool.asid_lock);
+ spin_lock(&per_cpu(asid_pool,oldcore).asid_lock);
if( retire_current && vmcb->guest_asid ) {
- svm_globals[oldcore].ASIDpool.asid[ vmcb->guest_asid & (ASID_MAX-1) ] = ASID_RETIRED;
+ per_cpu(asid_pool,oldcore).asid[vmcb->guest_asid & (ASID_MAX-1)] =
+ ASID_RETIRED;
}
- spin_unlock(&svm_globals[oldcore].ASIDpool.asid_lock);
- spin_lock(&svm_globals[newcore].ASIDpool.asid_lock);
+ spin_unlock(&per_cpu(asid_pool,oldcore).asid_lock);
+ spin_lock(&per_cpu(asid_pool,newcore).asid_lock);
if( asidpool_fetch_next( vmcb, newcore ) < 0 ) {
if (svm_dbg_on)
printk( "SVM: tlb(%ld)\n", cnt++ );
/* FLUSH the TLB and all retired slots are made available */
vmcb->tlb_control = 1;
for( i = 1; i < ASID_MAX; i++ ) {
- if( svm_globals[newcore].ASIDpool.asid[i] == ASID_RETIRED ) {
- svm_globals[newcore].ASIDpool.asid[i] = ASID_AVAILABLE;
+ if( per_cpu(asid_pool,newcore).asid[i] == ASID_RETIRED ) {
+ per_cpu(asid_pool,newcore).asid[i] = ASID_AVAILABLE;
}
}
/* Get the First slot available */
res = asidpool_fetch_next( vmcb, newcore ) > 0;
}
- spin_unlock(&svm_globals[newcore].ASIDpool.asid_lock);
+ spin_unlock(&per_cpu(asid_pool,newcore).asid_lock);
return res;
}
void asidpool_retire( struct vmcb_struct *vmcb, int core )
{
- spin_lock(&svm_globals[core].ASIDpool.asid_lock);
+ spin_lock(&per_cpu(asid_pool,core).asid_lock);
if( vmcb->guest_asid ) {
- svm_globals[core].ASIDpool.asid[ vmcb->guest_asid & (ASID_MAX-1) ] = ASID_RETIRED;
+ per_cpu(asid_pool,core).asid[vmcb->guest_asid & (ASID_MAX-1)] =
+ ASID_RETIRED;
}
- spin_unlock(&svm_globals[core].ASIDpool.asid_lock);
+ spin_unlock(&per_cpu(asid_pool,core).asid_lock);
}
-static inline void svm_inject_exception(struct vcpu *v, int trap, int ev, int error_code)
+static inline void svm_inject_exception(struct vcpu *v, int trap,
+ int ev, int error_code)
{
eventinj_t event;
struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
vmcb->eventinj = event;
}
-void stop_svm(void)
+static void stop_svm(void)
{
u32 eax, edx;
int cpu = smp_processor_id();
wrmsr(MSR_EFER, eax, edx);
/* release the HSA */
- free_host_save_area( svm_globals[cpu].hsa );
- free_host_save_area( svm_globals[cpu].scratch_hsa );
- svm_globals[cpu].hsa = NULL;
- svm_globals[cpu].hsa_pa = 0;
- svm_globals[cpu].scratch_hsa = NULL;
- svm_globals[cpu].scratch_hsa_pa = 0;
+ free_host_save_area(hsa[cpu]);
+ hsa[cpu] = NULL;
wrmsr(MSR_K8_VM_HSAVE_PA, 0, 0 );
+ /* free up the root vmcb */
+ free_vmcb(root_vmcb[cpu]);
+ root_vmcb[cpu] = NULL;
+ root_vmcb_pa[cpu] = 0;
+
printk("AMD SVM Extension is disabled.\n");
}
-int svm_initialize_guest_resources(struct vcpu *v)
-{
- svm_final_setup_guest(v);
- return 1;
-}
static void svm_store_cpu_guest_regs(
struct vcpu *v, struct cpu_user_regs *regs, unsigned long *crs)
}
}
-static void svm_load_cpu_guest_regs(
- struct vcpu *v, struct cpu_user_regs *regs)
+static int svm_paging_enabled(struct vcpu *v)
{
- svm_load_cpu_user_regs(v, regs);
+ unsigned long cr0;
+
+ cr0 = v->arch.hvm_svm.cpu_shadow_cr0;
+
+ return (cr0 & X86_CR0_PE) && (cr0 & X86_CR0_PG);
}
+
#define IS_CANO_ADDRESS(add) 1
static inline int long_mode_do_msr_read(struct cpu_user_regs *regs)
case MSR_SYSCALL_MASK:
msr_content = vmcb->sfmask;
break;
-
default:
return 0;
}
static inline int long_mode_do_msr_write(struct cpu_user_regs *regs)
{
- u64 msr_content = regs->eax | ((u64)regs->edx << 32);
+ u64 msr_content = regs->eax | ((u64)regs->edx << 32);
struct vcpu *vc = current;
struct vmcb_struct *vmcb = vc->arch.hvm_svm.vmcb;
/* LME: 0 -> 1 */
if ( msr_content & EFER_LME &&
- !test_bit(SVM_CPU_STATE_LME_ENABLED, &vc->arch.hvm_svm.cpu_state) )
+ !test_bit(SVM_CPU_STATE_LME_ENABLED, &vc->arch.hvm_svm.cpu_state))
{
if ( svm_paging_enabled(vc) ||
!test_bit(SVM_CPU_STATE_PAE_ENABLED,
return 1;
}
-int svm_realmode(struct vcpu *v)
+static int svm_realmode(struct vcpu *v)
{
unsigned long cr0 = v->arch.hvm_svm.cpu_shadow_cr0;
unsigned long eflags = v->arch.hvm_svm.vmcb->rflags;
return (eflags & X86_EFLAGS_VM) || !(cr0 & X86_CR0_PE);
}
-int svm_instruction_length(struct vcpu *v)
+static int svm_instruction_length(struct vcpu *v)
{
struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
unsigned long cr0 = vmcb->cr0, eflags = vmcb->rflags, mode;
return svm_instrlen(guest_cpu_user_regs(), mode);
}
-unsigned long svm_get_ctrl_reg(struct vcpu *v, unsigned int num)
+static unsigned long svm_get_ctrl_reg(struct vcpu *v, unsigned int num)
{
switch ( num )
{
}
+/* Make sure that xen intercepts any FP accesses from current */
+static void svm_stts(struct vcpu *v)
+{
+ struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
+
+ /*
+ * If the guest does not have TS enabled then we must cause and handle an
+ * exception on first use of the FPU. If the guest *does* have TS enabled
+ * then this is not necessary: no FPU activity can occur until the guest
+ * clears CR0.TS, and we will initialise the FPU when that happens.
+ */
+ if ( !(v->arch.hvm_svm.cpu_shadow_cr0 & X86_CR0_TS) )
+ {
+ v->arch.hvm_svm.vmcb->exception_intercepts |= EXCEPTION_BITMAP_NM;
+ vmcb->cr0 |= X86_CR0_TS;
+ }
+}
+
+
+static void svm_set_tsc_offset(struct vcpu *v, u64 offset)
+{
+ v->arch.hvm_svm.vmcb->tsc_offset = offset;
+}
+
+
/* SVM-specific intitialization code for VCPU application processors */
-void svm_init_ap_context(struct vcpu_guest_context *ctxt,
- int vcpuid, int trampoline_vector)
+static void svm_init_ap_context(struct vcpu_guest_context *ctxt,
+ int vcpuid, int trampoline_vector)
{
int i;
struct vcpu *v, *bsp = current;
* the code. We will execute this code in real mode.
*/
ctxt->user_regs.eip = 0x0;
- ctxt->user_regs.cs = (trampoline_vector << 8);
+ ctxt->user_regs.cs = (trampoline_vector << 8);
ctxt->flags = VGCF_HVM_GUEST;
}
*(u16 *)(hypercall_page + (__HYPERVISOR_iret * 32)) = 0x0b0f; /* ud2 */
}
-int start_svm(void)
-{
- u32 eax, ecx, edx;
- u32 phys_hsa_lo, phys_hsa_hi;
- u64 phys_hsa;
- int cpu = smp_processor_id();
-
- /* Xen does not fill x86_capability words except 0. */
- ecx = cpuid_ecx(0x80000001);
- boot_cpu_data.x86_capability[5] = ecx;
-
- if (!(test_bit(X86_FEATURE_SVME, &boot_cpu_data.x86_capability)))
- return 0;
- svm_globals[cpu].hsa = alloc_host_save_area();
- if (! svm_globals[cpu].hsa)
- return 0;
-
- rdmsr(MSR_EFER, eax, edx);
- eax |= EFER_SVME;
- wrmsr(MSR_EFER, eax, edx);
- asidpool_init( cpu );
- printk("AMD SVM Extension is enabled for cpu %d.\n", cpu );
-
- /* Initialize the HSA for this core */
- phys_hsa = (u64) virt_to_maddr( svm_globals[cpu].hsa );
- phys_hsa_lo = (u32) phys_hsa;
- phys_hsa_hi = (u32) (phys_hsa >> 32);
- wrmsr(MSR_K8_VM_HSAVE_PA, phys_hsa_lo, phys_hsa_hi);
- svm_globals[cpu].hsa_pa = phys_hsa;
-
- svm_globals[cpu].scratch_hsa = alloc_host_save_area();
- svm_globals[cpu].scratch_hsa_pa = (u64)virt_to_maddr( svm_globals[cpu].scratch_hsa );
-
- /* Setup HVM interfaces */
- hvm_funcs.disable = stop_svm;
-
- hvm_funcs.initialize_guest_resources = svm_initialize_guest_resources;
- hvm_funcs.relinquish_guest_resources = svm_relinquish_guest_resources;
- hvm_funcs.store_cpu_guest_regs = svm_store_cpu_guest_regs;
- hvm_funcs.load_cpu_guest_regs = svm_load_cpu_guest_regs;
- hvm_funcs.realmode = svm_realmode;
- hvm_funcs.paging_enabled = svm_paging_enabled;
- hvm_funcs.instruction_length = svm_instruction_length;
- hvm_funcs.get_guest_ctrl_reg = svm_get_ctrl_reg;
- hvm_funcs.init_ap_context = svm_init_ap_context;
-
- hvm_funcs.init_hypercall_page = svm_init_hypercall_page;
-
- hvm_enabled = 1;
-
- return 1;
-}
int svm_dbg_on = 0;
return 1;
}
-void save_svm_cpu_user_regs(struct vcpu *v, struct cpu_user_regs *ctxt)
+static void save_svm_cpu_user_regs(struct vcpu *v, struct cpu_user_regs *ctxt)
{
struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
ctxt->ds = vmcb->ds.sel;
}
-void svm_store_cpu_user_regs(struct cpu_user_regs *regs, struct vcpu *v)
+static void svm_store_cpu_user_regs(struct cpu_user_regs *regs, struct vcpu *v)
{
struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
}
/* XXX Use svm_load_cpu_guest_regs instead */
-void svm_load_cpu_user_regs(struct vcpu *v, struct cpu_user_regs *regs)
+static void svm_load_cpu_user_regs(struct vcpu *v, struct cpu_user_regs *regs)
{
struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
u32 *intercepts = &v->arch.hvm_svm.vmcb->exception_intercepts;
*intercepts &= ~EXCEPTION_BITMAP_DB;
}
-int svm_paging_enabled(struct vcpu *v)
+static void svm_load_cpu_guest_regs(
+ struct vcpu *v, struct cpu_user_regs *regs)
{
- unsigned long cr0;
-
- cr0 = v->arch.hvm_svm.cpu_shadow_cr0;
-
- return (cr0 & X86_CR0_PE) && (cr0 & X86_CR0_PG);
+ svm_load_cpu_user_regs(v, regs);
}
-/* Make sure that xen intercepts any FP accesses from current */
-void svm_stts(struct vcpu *v)
-{
- struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
-
- /* FPU state already dirty? Then no need to setup_fpu() lazily. */
- if ( test_bit(_VCPUF_fpu_dirtied, &v->vcpu_flags) )
- return;
-
- /*
- * If the guest does not have TS enabled then we must cause and handle an
- * exception on first use of the FPU. If the guest *does* have TS enabled
- * then this is not necessary: no FPU activity can occur until the guest
- * clears CR0.TS, and we will initialise the FPU when that happens.
- */
- if ( !(v->arch.hvm_svm.cpu_shadow_cr0 & X86_CR0_TS) )
- {
- v->arch.hvm_svm.vmcb->exception_intercepts |= EXCEPTION_BITMAP_NM;
- vmcb->cr0 |= X86_CR0_TS;
- }
-}
static void arch_svm_do_launch(struct vcpu *v)
{
{
u16 cs_sel = regs->cs;
/*
- * This is the launch of an AP; set state so that we begin executing
+ * This is the launch of an AP; set state so that we begin executing
* the trampoline code in real-mode.
- */
+ */
svm_do_vmmcall_reset_to_realmode(v, regs);
/* Adjust the state to execute the trampoline code.*/
v->arch.hvm_svm.vmcb->rip = 0;
}
}
+
static void svm_ctxt_switch_from(struct vcpu *v)
{
svm_freeze_time(v);
static void svm_ctxt_switch_to(struct vcpu *v)
{
-#if __x86_64__
+#ifdef __x86_64__
/*
* This is required, because VMRUN does consistency check
* and some of the DOM0 selectors are pointing to
#endif
}
-void svm_final_setup_guest(struct vcpu *v)
+
+static void svm_final_setup_guest(struct vcpu *v)
{
struct domain *d = v->domain;
struct vcpu *vc;
* Put the domain in shadow mode even though we're going to be using
* the shared 1:1 page table initially. It shouldn't hurt
*/
- shadow_mode_enable(d,
- SHM_enable|SHM_refcounts|
+ shadow_mode_enable(d, SHM_enable|SHM_refcounts|
SHM_translate|SHM_external|SHM_wr_pt_pte);
}
+static int svm_initialize_guest_resources(struct vcpu *v)
+{
+ svm_final_setup_guest(v);
+ return 1;
+}
+
+
+int start_svm(void)
+{
+ u32 eax, ecx, edx;
+ u32 phys_hsa_lo, phys_hsa_hi;
+ u64 phys_hsa;
+ int cpu = smp_processor_id();
+
+ /* Xen does not fill x86_capability words except 0. */
+ ecx = cpuid_ecx(0x80000001);
+ boot_cpu_data.x86_capability[5] = ecx;
+
+ if (!(test_bit(X86_FEATURE_SVME, &boot_cpu_data.x86_capability)))
+ return 0;
+
+ if (!(hsa[cpu] = alloc_host_save_area()))
+ return 0;
+
+ rdmsr(MSR_EFER, eax, edx);
+ eax |= EFER_SVME;
+ wrmsr(MSR_EFER, eax, edx);
+ asidpool_init( cpu );
+ printk("AMD SVM Extension is enabled for cpu %d.\n", cpu );
+
+ /* Initialize the HSA for this core */
+ phys_hsa = (u64) virt_to_maddr(hsa[cpu]);
+ phys_hsa_lo = (u32) phys_hsa;
+ phys_hsa_hi = (u32) (phys_hsa >> 32);
+ wrmsr(MSR_K8_VM_HSAVE_PA, phys_hsa_lo, phys_hsa_hi);
+
+ if (!(root_vmcb[cpu] = alloc_vmcb()))
+ return 0;
+ root_vmcb_pa[cpu] = virt_to_maddr(root_vmcb[cpu]);
+
+ if (cpu == 0)
+ setup_vmcb_dump();
+
+ /* Setup HVM interfaces */
+ hvm_funcs.disable = stop_svm;
+
+ hvm_funcs.initialize_guest_resources = svm_initialize_guest_resources;
+ hvm_funcs.relinquish_guest_resources = svm_relinquish_guest_resources;
+
+ hvm_funcs.store_cpu_guest_regs = svm_store_cpu_guest_regs;
+ hvm_funcs.load_cpu_guest_regs = svm_load_cpu_guest_regs;
+
+ hvm_funcs.realmode = svm_realmode;
+ hvm_funcs.paging_enabled = svm_paging_enabled;
+ hvm_funcs.instruction_length = svm_instruction_length;
+ hvm_funcs.get_guest_ctrl_reg = svm_get_ctrl_reg;
+
+ hvm_funcs.stts = svm_stts;
+ hvm_funcs.set_tsc_offset = svm_set_tsc_offset;
+
+ hvm_funcs.init_ap_context = svm_init_ap_context;
+ hvm_funcs.init_hypercall_page = svm_init_hypercall_page;
+
+ hvm_enabled = 1;
+
+ return 1;
+}
+
+
static void svm_relinquish_guest_resources(struct domain *d)
{
- extern void destroy_vmcb(struct arch_svm_struct *); /* XXX */
struct vcpu *v;
for_each_vcpu ( d, v )
}
+static void svm_migrate_timers(struct vcpu *v)
+{
+ struct periodic_time *pt =
+ &(v->domain->arch.hvm_domain.pl_time.periodic_tm);
+
+ if ( pt->enabled ) {
+ migrate_timer( &pt->timer, v->processor );
+ migrate_timer( &v->arch.hvm_svm.hlt_timer, v->processor );
+ }
+ if ( hvm_apic_support(v->domain) && VLAPIC( v ))
+ migrate_timer( &(VLAPIC(v)->vlapic_timer ), v->processor );
+}
+
+
void arch_svm_do_resume(struct vcpu *v)
{
/* pinning VCPU to a different core? */
if ( v->arch.hvm_svm.launch_core == smp_processor_id()) {
- svm_do_resume( v );
+ hvm_do_resume( v );
reset_stack_and_jump( svm_asm_do_resume );
}
else {
v->arch.hvm_svm.launch_core, smp_processor_id() );
v->arch.hvm_svm.launch_core = smp_processor_id();
svm_migrate_timers( v );
- svm_do_resume( v );
+ hvm_do_resume( v );
reset_stack_and_jump( svm_asm_do_resume );
}
}
-void svm_migrate_timers(struct vcpu *v)
-{
- struct periodic_time *pt = &(v->domain->arch.hvm_domain.pl_time.periodic_tm);
-
- if ( pt->enabled ) {
- migrate_timer( &pt->timer, v->processor );
- migrate_timer( &v->arch.hvm_svm.hlt_timer, v->processor );
- }
- if ( hvm_apic_support(v->domain) && VLAPIC( v ))
- migrate_timer( &(VLAPIC(v)->vlapic_timer ), v->processor );
-}
-
static int svm_do_page_fault(unsigned long va, struct cpu_user_regs *regs)
{
inst_len = svm_instruction_length(v);
if (inst_len == -1)
{
- printf("%s: INST_LEN - Unable to decode properly.\n", __func__);
+ printf("%s: INST_LEN - Unable to decode properly\n", __func__);
domain_crash_synchronous();
}
case SVM_REG_ESP:
reg_p = (unsigned long *)&vmcb->rsp;
break;
-#if __x86_64__
+#ifdef __x86_64__
case SVM_REG_R8:
reg_p = (unsigned long *)®s->r8;
break;
unsigned long *reg_p = 0;
unsigned int gpreg = 0;
unsigned long eip;
- int inst_len;
+ int inst_len;
int index;
struct vmcb_struct *vmcb;
u8 buffer[MAX_INST_LEN];
case 0xf2: /* REPNZ */
case 0xf0: /* LOCK */
case 0x66: /* data32 */
-#if __x86_64__
+#ifdef __x86_64__
/* REX prefixes */
case 0x40:
case 0x41:
info.bytes = vmcb->exitinfo1;
- /* If we're in long mode, we shouldn't check the segment presence and limit */
+ /* If we're in long mode, we shouldn't check the segment presence & limit */
long_mode = vmcb->cs.attributes.fields.l && vmcb->efer & EFER_LMA;
/* d field of cs.attributes is 1 for 32-bit, 0 for 16 or 64 bit.
* arch->shadow_table should hold the next CR3 for shadow
*/
- HVM_DBG_LOG(DBG_LEVEL_VMMU, "Update CR3 value = %lx, mfn = %lx",
+ HVM_DBG_LOG(DBG_LEVEL_VMMU,
+ "Update CR3 value = %lx, mfn = %lx",
v->arch.hvm_svm.cpu_cr3, mfn);
#endif
}
* it must enable PG after that, and it is a 32-bit PAE
* guest */
- if ( !shadow_set_guest_paging_levels(v->domain, PAGING_L3) )
+ if ( !shadow_set_guest_paging_levels(v->domain, PAGING_L3))
{
printk("Unsupported guest paging levels\n");
domain_crash_synchronous();
}
else
{
- if ( !shadow_set_guest_paging_levels(v->domain,
- PAGING_L4) )
+ if ( !shadow_set_guest_paging_levels(v->domain, PAGING_L4))
{
printk("Unsupported guest paging levels\n");
domain_crash_synchronous();
ASSERT(vmcb);
inst_copy_from_guest(buffer, svm_rip2pointer(vmcb), sizeof(buffer));
- /* get index to first actual instruction byte - as we will need to know where the
- * prefix lives later on
- */
+
+ /* get index to first actual instruction byte - as we will need to know
+ where the prefix lives later on */
index = skip_prefix_bytes(buffer, sizeof(buffer));
if (type == TYPE_MOV_TO_CR)
switch (regs->ecx)
{
case MSR_IA32_TIME_STAMP_COUNTER:
- svm_set_guest_time(v, msr_content);
+ hvm_set_guest_time(v, msr_content);
break;
case MSR_IA32_SYSENTER_CS:
vmcb->sysenter_cs = msr_content;
/* check for interrupt not handled or new interrupt */
if ( vmcb->vintr.fields.irq || cpu_has_pending_irq(v) )
- return;
+ return;
if ( !v->vcpu_id )
next_pit = get_scheduled(v, pt->irq, pt);
* have cache-snooping that solves it anyways. -- Mats P.
*/
- /* Tell the user that we did this - just in case someone runs some really weird
- * operating system and wants to know why it's not working as it should...
+ /* Tell the user that we did this - just in case someone runs some really
+ * weird operating system and wants to know why it's not working...
*/
printk("INVD instruction intercepted - ignored\n");
*/
if (inst_copy_from_guest(opcode, svm_rip2pointer(vmcb), length) < length)
{
- printk("svm_handle_invlpg (): Error reading memory %d bytes\n", length);
+ printk("svm_handle_invlpg (): Error reading memory %d bytes\n",
+ length);
__hvm_bug(regs);
}
__asm__ __volatile__ ("\tmov %%cr0,%0\n"
"\tmov %%cr3,%1\n"
- : "=r" (cr0), "=r"(cr3));
+ : "=r" (cr0), "=r"(cr3));
printf("%s: pt = %lx, cr3 = %lx, cr0 = %lx\n", __func__, pt, cr3, cr0);
}
spte = l1e_empty();
- /* This is actually overkill - we only need to make sure the hl2 is in-sync. */
+ /* This is actually overkill - we only need to ensure the hl2 is in-sync.*/
shadow_sync_va(v, gva);
gpte.l1 = 0;
- __copy_from_user(&gpte, &linear_pg_table[ l1_linear_offset(gva) ], sizeof(gpte) );
+ __copy_from_user(&gpte, &linear_pg_table[ l1_linear_offset(gva) ],
+ sizeof(gpte) );
printk( "G-PTE = %x, flags=%x\n", gpte.l1, l1e_get_flags(gpte) );
- __copy_from_user( &spte, &phys_to_machine_mapping[ l1e_get_pfn( gpte ) ],
+ __copy_from_user( &spte, &phys_to_machine_mapping[ l1e_get_pfn( gpte ) ],
sizeof(spte) );
printk( "S-PTE = %x, flags=%x\n", spte.l1, l1e_get_flags(spte));
}
#endif /* SVM_WALK_GUEST_PAGES */
+
+
+
asmlinkage void svm_vmexit_handler(struct cpu_user_regs regs)
{
unsigned int exit_reason;
vmcb->tlb_control = 1;
+
+ if (exit_reason == VMEXIT_INVALID)
+ {
+ svm_dump_vmcb(__func__, vmcb);
+ domain_crash_synchronous();
+ }
+
#ifdef SVM_EXTRA_DEBUG
{
#if defined(__i386__)
{
if (svm_paging_enabled(v) && !mmio_space(gva_to_gpa(vmcb->exitinfo2)))
{
- printk("I%08ld,ExC=%s(%d),IP=%x:%llx,I1=%llx,I2=%llx,INT=%llx, gpa=%llx\n",
- intercepts_counter,
+ printk("I%08ld,ExC=%s(%d),IP=%x:%llx,I1=%llx,I2=%llx,INT=%llx, "
+ "gpa=%llx\n", intercepts_counter,
exit_reasons[exit_reason], exit_reason, regs.cs,
(unsigned long long) regs.rip,
(unsigned long long) vmcb->exitinfo1,
}
#endif /* SVM_EXTRA_DEBUG */
- if (exit_reason == -1)
- {
- svm_dump_vmcb(__func__, vmcb);
- printk("%s: exit_reason == -1 - Did someone clobber the VMCB\n",
- __func__);
- domain_crash_synchronous();
- }
perfc_incra(svmexits, exit_reason);
eip = vmcb->rip;
#ifdef SVM_EXTRA_DEBUG
if (do_debug)
{
- printk("%s: Done switch on vmexit_code\n", __func__);
+ printk("%s: Done switch on vmexit_code\n", __func__);
svm_dump_regs(__func__, ®s);
}
v->arch.hvm_svm.asid_core = v->arch.hvm_svm.launch_core;
clear_bit( ARCH_SVM_VMCB_ASSIGN_ASID, &v->arch.hvm_svm.flags );
}
-
- /* make sure the HSA is set for the current core */
- set_hsa_to_guest( &v->arch.hvm_svm );
}
/*
#include <xen/event.h>
#include <xen/kernel.h>
#include <xen/domain_page.h>
+#include <xen/keyhandler.h>
-extern struct svm_percore_globals svm_globals[];
extern int svm_dbg_on;
extern int asidpool_assign_next( struct vmcb_struct *vmcb, int retire_current,
int oldcore, int newcore);
-extern void set_hsa_to_guest( struct arch_svm_struct *arch_svm );
-
-#define round_pgdown(_p) ((_p)&PAGE_MASK) /* coped from domain.c */
#define GUEST_SEGMENT_LIMIT 0xffffffff
#define IOPM_SIZE (12 * 1024)
#define MSRPM_SIZE (8 * 1024)
+/* VMCBs and HSAs are architecturally defined to be a 4K page each */
+#define VMCB_ORDER 0
+#define HSA_ORDER 0
+
+
struct vmcb_struct *alloc_vmcb(void)
{
- struct vmcb_struct *vmcb = NULL;
- unsigned int order;
- order = get_order_from_bytes(sizeof(struct vmcb_struct));
- ASSERT(order >= 0);
- vmcb = alloc_xenheap_pages(order);
- ASSERT(vmcb);
+ struct vmcb_struct *vmcb = alloc_xenheap_pages(VMCB_ORDER);
- if (vmcb)
- memset(vmcb, 0, sizeof(struct vmcb_struct));
+ if (!vmcb) {
+ printk("Warning: failed to allocate vmcb.\n");
+ return NULL;
+ }
+ memset(vmcb, 0, (PAGE_SIZE << VMCB_ORDER));
return vmcb;
}
void free_vmcb(struct vmcb_struct *vmcb)
{
- unsigned int order;
-
- order = get_order_from_bytes(sizeof(struct vmcb_struct));
ASSERT(vmcb);
-
- if (vmcb)
- free_xenheap_pages(vmcb, order);
+ free_xenheap_pages(vmcb, VMCB_ORDER);
}
struct host_save_area *alloc_host_save_area(void)
{
- unsigned int order = 0;
- struct host_save_area *hsa = NULL;
-
- hsa = alloc_xenheap_pages(order);
- ASSERT(hsa);
+ struct host_save_area *hsa = alloc_xenheap_pages(HSA_ORDER);
- if (hsa)
- memset(hsa, 0, PAGE_SIZE);
+ if (!hsa) {
+ printk("Warning: failed to allocate vmcb.\n");
+ return NULL;
+ }
+ memset(hsa, 0, (PAGE_SIZE << HSA_ORDER));
return hsa;
}
void free_host_save_area(struct host_save_area *hsa)
{
- unsigned int order;
-
- order = get_order_from_bytes(PAGE_SIZE);
ASSERT(hsa);
-
- if (hsa)
- free_xenheap_pages(hsa, order);
+ free_xenheap_pages(hsa, HSA_ORDER);
}
vmcb->cs.sel = regs->cs;
vmcb->es.sel = regs->es;
vmcb->ss.sel = regs->ss;
- vmcb->ds.sel = regs->ds;
+ vmcb->ds.sel = regs->ds;
vmcb->fs.sel = regs->fs;
vmcb->gs.sel = regs->gs;
attrib.fields.g = 1; /* 4K pages in limit */
/* Data selectors */
- vmcb->es.attributes = attrib;
+ vmcb->es.attributes = attrib;
vmcb->ss.attributes = attrib;
vmcb->ds.attributes = attrib;
vmcb->fs.attributes = attrib;
/* CR3 is set in svm_final_setup_guest */
- __asm__ __volatile__ ("mov %%cr4,%0" : "=r" (crn) :);
+ __asm__ __volatile__ ("mov %%cr4,%0" : "=r" (crn) :);
crn &= ~(X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE);
arch_svm->cpu_shadow_cr4 = crn;
vmcb->cr4 = crn | SVM_CR4_HOST_MASK;
* construct the vmcb.
*/
-int construct_vmcb(struct arch_svm_struct *arch_svm, struct cpu_user_regs *regs)
+int construct_vmcb(struct arch_svm_struct *arch_svm,
+ struct cpu_user_regs *regs)
{
int error;
long rc=0;
}
/* update the HSA for the current Core */
+#if 0
set_hsa_to_guest( arch_svm );
+#endif
arch_svm->vmcb_pa = (u64) virt_to_maddr(arch_svm->vmcb);
if ((error = construct_vmcb_controls(arch_svm)))
ASSERT(vmcb);
/* Update CR3, GDT, LDT, TR */
- svm_stts(v);
+ hvm_stts(v);
/* current core is the one we intend to perform the VMRUN on */
v->arch.hvm_svm.launch_core = v->arch.hvm_svm.asid_core = core;
printk("%s: phys_table = %lx\n", __func__, pt);
}
- if ( svm_paging_enabled(v) )
- vmcb->cr3 = pagetable_get_paddr(v->arch.guest_table);
- else
- vmcb->cr3 = pagetable_get_paddr(v->domain->arch.phys_table);
+ /* At launch we always use the phys_table */
+ vmcb->cr3 = pagetable_get_paddr(v->domain->arch.phys_table);
if (svm_dbg_on)
{
v->arch.hvm_svm.saved_irq_vector = -1;
- svm_set_guest_time(v, 0);
+ hvm_set_guest_time(v, 0);
if (svm_dbg_on)
svm_dump_vmcb(__func__, vmcb);
}
-void set_hsa_to_guest( struct arch_svm_struct *arch_svm )
-{
- arch_svm->host_save_pa = svm_globals[ smp_processor_id() ].scratch_hsa_pa;
-}
-/*
- * Resume the guest.
- */
-/* XXX svm_do_resume and vmx_do_resume are remarkably similar; could
- they be unified? */
-void svm_do_resume(struct vcpu *v)
-{
- struct periodic_time *pt = &v->domain->arch.hvm_domain.pl_time.periodic_tm;
- ioreq_t *p;
-
- svm_stts(v);
-
- /* pick up the elapsed PIT ticks and re-enable pit_timer */
- if ( pt->enabled && pt->first_injected ) {
- if ( v->arch.hvm_vcpu.guest_time ) {
- svm_set_guest_time(v, v->arch.hvm_vcpu.guest_time);
- v->arch.hvm_vcpu.guest_time = 0;
- }
- pickup_deactive_ticks(pt);
- }
-
- p = &get_vio(v->domain, v->vcpu_id)->vp_ioreq;
- wait_on_xen_event_channel(v->arch.hvm.xen_port,
- p->state != STATE_IOREQ_READY &&
- p->state != STATE_IOREQ_INPROCESS);
- if ( p->state == STATE_IORESP_READY )
- hvm_io_assist(v);
- if ( p->state != STATE_INVALID ) {
- printf("Weird HVM iorequest state %d.\n", p->state);
- domain_crash(v->domain);
- }
-}
-
-void svm_launch_fail(unsigned long eflags)
-{
- BUG();
-}
-
-
-void svm_resume_fail(unsigned long eflags)
-{
- BUG();
-}
-
-
-void svm_dump_sel(char *name, segment_selector_t *s)
+static void svm_dump_sel(char *name, segment_selector_t *s)
{
printf("%s: sel=0x%04x, attr=0x%04x, limit=0x%08x, base=0x%016llx\n",
name, s->sel, s->attributes.bytes, s->limit,
- (unsigned long long)s->base);
+ (unsigned long long)s->base);
}
printf("Size of VMCB = %d, address = %p\n",
(int) sizeof(struct vmcb_struct), vmcb);
- printf("cr_intercepts = 0x%08x dr_intercepts = 0x%08x exception_intercepts "
- "= 0x%08x\n", vmcb->cr_intercepts, vmcb->dr_intercepts,
- vmcb->exception_intercepts);
+ printf("cr_intercepts = 0x%08x dr_intercepts = 0x%08x "
+ "exception_intercepts = 0x%08x\n",
+ vmcb->cr_intercepts, vmcb->dr_intercepts,
+ vmcb->exception_intercepts);
printf("general1_intercepts = 0x%08x general2_intercepts = 0x%08x\n",
vmcb->general1_intercepts, vmcb->general2_intercepts);
printf("iopm_base_pa = %016llx msrpm_base_pa = 0x%016llx tsc_offset = "
printf("DR6 = 0x%016llx, DR7 = 0x%016llx\n",
(unsigned long long) vmcb->dr6, (unsigned long long) vmcb->dr7);
printf("CSTAR = 0x%016llx SFMask = 0x%016llx\n",
- (unsigned long long) vmcb->cstar, (unsigned long long) vmcb->sfmask);
+ (unsigned long long) vmcb->cstar,
+ (unsigned long long) vmcb->sfmask);
printf("KernGSBase = 0x%016llx PAT = 0x%016llx \n",
(unsigned long long) vmcb->kerngsbase,
(unsigned long long) vmcb->g_pat);
svm_dump_sel("TR", &vmcb->tr);
}
+static void vmcb_dump(unsigned char ch)
+{
+ struct domain *d;
+ struct vcpu *v;
+
+ printk("*********** VMCB Areas **************\n");
+ for_each_domain(d) {
+ printk("\n>>> Domain %d <<<\n", d->domain_id);
+ for_each_vcpu(d, v) {
+
+ /*
+ * Presumably, if a domain is not an HVM guest,
+ * the very first CPU will not pass this test
+ */
+ if (!hvm_guest(v)) {
+ printk("\t\tNot HVM guest\n");
+ break;
+ }
+ printk("\tVCPU %d\n", v->vcpu_id);
+
+ svm_dump_vmcb("key_handler", v->arch.hvm_svm.vmcb);
+ }
+ }
+
+ printk("**************************************\n");
+}
+
+void setup_vmcb_dump(void)
+{
+ register_keyhandler('v', vmcb_dump, "dump AMD-V VMCBs");
+}
+
/*
* Local variables:
* mode: C
movl VCPU_svm_vmcb(%ebx), %ecx
movl 24(%esp), %eax
movl %eax, VMCB_rax(%ecx)
- movl VCPU_svm_hsa_pa(%ebx), %eax
+ movl VCPU_processor(%ebx), %eax
+ movl root_vmcb_pa(,%eax,8), %eax
VMSAVE
movl VCPU_svm_vmcb_pa(%ebx), %eax
GET_CURRENT(%eax)
- movl VCPU_svm_hsa_pa(%eax), %eax
+ movl VCPU_processor(%eax), %eax
+ movl root_vmcb_pa(,%eax,8), %eax
VMLOAD
HVM_SAVE_ALL_NOSEGREGS
svm_test_all_events:
GET_CURRENT(%ebx)
pushl %ebx
- call svm_do_resume
+ call hvm_do_resume
addl $4, %esp
/*test_all_events:*/
xorl %ecx,%ecx
movq VCPU_svm_vmcb(%rbx), %rcx
movq UREGS_rax(%rsp), %rax
movq %rax, VMCB_rax(%rcx)
- movq VCPU_svm_hsa_pa(%rbx), %rax
+ leaq root_vmcb_pa(%rip), %rax
+ movl VCPU_processor(%rbx), %ecx
+ shll $3, %ecx
+ addq %rcx, %rax
VMSAVE
movq VCPU_svm_vmcb_pa(%rbx), %rax
VMLOAD
VMRUN
VMSAVE
- /* rax is the only register we're allowed to touch here... */
+ HVM_SAVE_ALL_NOSEGREGS
- GET_CURRENT(%rax)
- movq VCPU_svm_hsa_pa(%rax), %rax
+ GET_CURRENT(%rbx)
+ movl VCPU_processor(%rbx), %ecx
+ leaq root_vmcb_pa(%rip), %rax
+ shll $3, %ecx
+ addq %rcx, %rax
VMLOAD
- HVM_SAVE_ALL_NOSEGREGS
STGI
call svm_vmexit_handler
jmp svm_asm_do_resume
svm_test_all_events:
GET_CURRENT(%rbx)
movq %rbx, %rdi
- call svm_do_resume
+ call hvm_do_resume
/*test_all_events:*/
cli # tests must not race interrupts
/*test_softirqs:*/
case APIC_ESR:
vlapic->err_write_count = 0;
- *result = vlapic_get_reg(vlapic, offset);
+ *result = vlapic_get_reg(vlapic, offset);
break;
default:
#include <asm/hvm/vlapic.h>
#include <public/hvm/ioreq.h>
-#define BSP_CPU(v) (!(v->vcpu_id))
-
-static inline
-void __set_tsc_offset(u64 offset)
-{
- __vmwrite(TSC_OFFSET, offset);
-#if defined (__i386__)
- __vmwrite(TSC_OFFSET_HIGH, offset >> 32);
-#endif
-}
-
-void set_guest_time(struct vcpu *v, u64 gtime)
-{
- u64 host_tsc;
-
- rdtscll(host_tsc);
-
- v->arch.hvm_vcpu.cache_tsc_offset = gtime - host_tsc;
- __set_tsc_offset(v->arch.hvm_vcpu.cache_tsc_offset);
-}
-
-static inline void
-interrupt_post_injection(struct vcpu * v, int vector, int type)
-{
- struct periodic_time *pt = &(v->domain->arch.hvm_domain.pl_time.periodic_tm);
-
- if ( is_pit_irq(v, vector, type) ) {
- if ( !pt->first_injected ) {
- pt->pending_intr_nr = 0;
- pt->last_plt_gtime = hvm_get_guest_time(v);
- pt->scheduled = NOW() + pt->period;
- set_timer(&pt->timer, pt->scheduled);
- pt->first_injected = 1;
- } else {
- pt->pending_intr_nr--;
- pt->last_plt_gtime += pt->period_cycles;
- set_guest_time(v, pt->last_plt_gtime);
- pit_time_fired(v, pt->priv);
- }
- }
-
- switch(type)
- {
- case APIC_DM_EXTINT:
- break;
-
- default:
- vlapic_post_injection(v, vector, type);
- break;
- }
-}
static inline void
enable_irq_window(struct vcpu *v)
if (likely(!has_ext_irq)) return;
- if (unlikely(is_interruptibility_state())) { /* pre-cleared for emulated instruction */
+ if (unlikely(is_interruptibility_state())) {
+ /* pre-cleared for emulated instruction */
enable_irq_window(v);
HVM_DBG_LOG(DBG_LEVEL_1, "interruptibility");
return;
return;
}
- highest_vector = cpu_get_interrupt(v, &intr_type);
+ highest_vector = cpu_get_interrupt(v, &intr_type);
switch (intr_type) {
case APIC_DM_EXTINT:
case APIC_DM_FIXED:
BUG();
break;
}
-
- interrupt_post_injection(v, highest_vector, intr_type);
+
+ hvm_interrupt_post(v, highest_vector, intr_type);
return;
}
-void vmx_do_resume(struct vcpu *v)
-{
- ioreq_t *p;
- struct periodic_time *pt = &v->domain->arch.hvm_domain.pl_time.periodic_tm;
-
- vmx_stts();
-
- /* pick up the elapsed PIT ticks and re-enable pit_timer */
- if ( pt->enabled && pt->first_injected ) {
- if ( v->arch.hvm_vcpu.guest_time ) {
- set_guest_time(v, v->arch.hvm_vcpu.guest_time);
- v->arch.hvm_vcpu.guest_time = 0;
- }
- pickup_deactive_ticks(pt);
- }
-
- p = &get_vio(v->domain, v->vcpu_id)->vp_ioreq;
- wait_on_xen_event_channel(v->arch.hvm.xen_port,
- p->state != STATE_IOREQ_READY &&
- p->state != STATE_IOREQ_INPROCESS);
- if ( p->state == STATE_IORESP_READY )
- hvm_io_assist(v);
- if ( p->state != STATE_INVALID ) {
- printf("Weird HVM iorequest state %d.\n", p->state);
- domain_crash(v->domain);
- }
-}
-
/*
* Local variables:
* mode: C
error |= __vmwrite(CR4_READ_SHADOW, cr4);
- vmx_stts();
+ hvm_stts(v);
if(hvm_apic_support(v->domain))
vlapic_init(v);
v->arch.schedule_tail = arch_vmx_do_resume;
/* init guest tsc to start from 0 */
- set_guest_time(v, 0);
+ hvm_set_guest_time(v, 0);
}
/*
vmx_set_host_env(v);
}
- vmx_do_resume(v);
+ hvm_do_resume(v);
reset_stack_and_jump(vmx_asm_do_vmentry);
}
printk("**************************************\n");
}
-static int __init setup_vmcs_dump(void)
+void setup_vmcs_dump(void)
{
register_keyhandler('v', vmcs_dump, "dump Intel's VMCS");
- return 0;
}
-__initcall(setup_vmcs_dump);
/*
* Local variables:
return 0; /* dummy */
}
+
+
+/* Make sure that xen intercepts any FP accesses from current */
+static void vmx_stts(struct vcpu *v)
+{
+ unsigned long cr0;
+
+ /* VMX depends on operating on the current vcpu */
+ ASSERT(v == current);
+
+ /*
+ * If the guest does not have TS enabled then we must cause and handle an
+ * exception on first use of the FPU. If the guest *does* have TS enabled
+ * then this is not necessary: no FPU activity can occur until the guest
+ * clears CR0.TS, and we will initialise the FPU when that happens.
+ */
+ __vmread_vcpu(v, CR0_READ_SHADOW, &cr0);
+ if ( !(cr0 & X86_CR0_TS) )
+ {
+ __vmread_vcpu(v, GUEST_CR0, &cr0);
+ __vmwrite(GUEST_CR0, cr0 | X86_CR0_TS);
+ __vm_set_bit(EXCEPTION_BITMAP, EXCEPTION_BITMAP_NM);
+ }
+}
+
+
+static void vmx_set_tsc_offset(struct vcpu *v, u64 offset)
+{
+ /* VMX depends on operating on the current vcpu */
+ ASSERT(v == current);
+
+ __vmwrite(TSC_OFFSET, offset);
+#if defined (__i386__)
+ __vmwrite(TSC_OFFSET_HIGH, offset >> 32);
+#endif
+}
+
+
+
/* SMP VMX guest support */
static void vmx_init_ap_context(struct vcpu_guest_context *ctxt,
int vcpuid, int trampoline_vector)
hvm_funcs.instruction_length = vmx_instruction_length;
hvm_funcs.get_guest_ctrl_reg = vmx_get_ctrl_reg;
+ hvm_funcs.stts = vmx_stts;
+ hvm_funcs.set_tsc_offset = vmx_set_tsc_offset;
+
hvm_funcs.init_ap_context = vmx_init_ap_context;
hvm_funcs.init_hypercall_page = vmx_init_hypercall_page;
set_in_cr4(X86_CR4_VMXE);
vmx_init_vmcs_config();
+
+ setup_vmcs_dump();
if ( (vmcs = vmx_alloc_host_vmcs()) == NULL )
{
if ( input == CPUID_LEAF_0x1 )
{
/* mask off reserved bits */
- ecx &= ~VMX_VCPU_CPUID_L1_ECX_RESERVED;
+ ecx &= ~VMX_VCPU_CPUID_L1_ECX_RESERVED;
if ( !hvm_apic_support(v->domain) ||
!vlapic_global_enabled((VLAPIC(v))) )
#if CONFIG_PAGING_LEVELS < 3
edx &= ~(bitmaskof(X86_FEATURE_PAE) |
bitmaskof(X86_FEATURE_PSE) |
- bitmaskof(X86_FEATURE_PSE36));
+ bitmaskof(X86_FEATURE_PSE36));
#else
if ( v->domain->arch.ops->guest_paging_levels == PAGING_L2 )
{
shadow_invlpg(v, va);
}
+
static int check_for_null_selector(unsigned long eip)
{
unsigned char inst[MAX_INST_LEN];
switch (regs->ecx) {
case MSR_IA32_TIME_STAMP_COUNTER:
- set_guest_time(v, msr_content);
+ hvm_set_guest_time(v, msr_content);
break;
case MSR_IA32_SYSENTER_CS:
__vmwrite(GUEST_SYSENTER_CS, msr_content);
ENTRY(vmx_asm_do_vmentry)
GET_CURRENT(%ebx)
pushl %ebx
- call vmx_do_resume
+ call hvm_do_resume
addl $4, %esp
cli # tests must not race interrupts
ENTRY(vmx_asm_do_vmentry)
GET_CURRENT(%rbx)
movq %rbx, %rdi
- call vmx_do_resume
+ call hvm_do_resume
cli # tests must not race interrupts
movl VCPU_processor(%rbx),%eax
BLANK();
OFFSET(VCPU_svm_vmcb_pa, struct vcpu, arch.hvm_svm.vmcb_pa);
- OFFSET(VCPU_svm_hsa_pa, struct vcpu, arch.hvm_svm.host_save_pa);
OFFSET(VCPU_svm_vmcb, struct vcpu, arch.hvm_svm.vmcb);
OFFSET(VCPU_svm_vmexit_tsc, struct vcpu, arch.hvm_svm.vmexit_tsc);
BLANK();
BLANK();
OFFSET(VCPU_svm_vmcb_pa, struct vcpu, arch.hvm_svm.vmcb_pa);
- OFFSET(VCPU_svm_hsa_pa, struct vcpu, arch.hvm_svm.host_save_pa);
OFFSET(VCPU_svm_vmcb, struct vcpu, arch.hvm_svm.vmcb);
OFFSET(VCPU_svm_vmexit_tsc, struct vcpu, arch.hvm_svm.vmexit_tsc);
BLANK();
int (*instruction_length)(struct vcpu *v);
unsigned long (*get_guest_ctrl_reg)(struct vcpu *v, unsigned int num);
+ /*
+ * Update specifics of the guest state:
+ * 1) TS bit in guest cr0
+ * 2) TSC offset in guest
+ */
+ void (*stts)(struct vcpu *v);
+ void (*set_tsc_offset)(struct vcpu *v, u64 offset);
+
void (*init_ap_context)(struct vcpu_guest_context *ctxt,
int vcpuid, int trampoline_vector);
return 0; /* force to fail */
}
+extern void hvm_stts(struct vcpu *v);
+extern void hvm_set_guest_time(struct vcpu *v, u64 gtime);
+extern void hvm_do_resume(struct vcpu *v);
+
static inline void
hvm_init_ap_context(struct vcpu_guest_context *ctxt,
int vcpuid, int trampoline_vector)
#endif
extern void handle_mmio(unsigned long, unsigned long);
+extern void hvm_interrupt_post(struct vcpu *v, int vector, int type);
extern void hvm_io_assist(struct vcpu *v);
extern void pic_irq_request(void *data, int level);
extern void hvm_pic_assist(struct vcpu *v);
#include <asm/hvm/svm/vmcb.h>
#include <asm/i387.h>
-extern void asidpool_retire( struct vmcb_struct *vmcb, int core );
-
-extern void svm_asm_vmexit_handler(struct cpu_user_regs);
-extern void svm_setup_function_table(struct vcpu *v);
-
-extern int vmcb_size;
-extern unsigned int cpu_rev;
-
-extern void svm_stop(void);
-extern void svm_save_cpu_user_regs(struct vcpu *v, struct cpu_user_regs *regs);
-extern void svm_load_cpu_user_regs(struct vcpu *v, struct cpu_user_regs *regs);
-extern void svm_vmread(struct vcpu *v, int index, unsigned long *value);
-extern void svm_vmwrite(struct vcpu *v, int index, unsigned long value);
-extern void svm_final_setup_guest(struct vcpu *v);
-extern int svm_paging_enabled(struct vcpu *v);
+extern void asidpool_retire(struct vmcb_struct *vmcb, int core);
extern void svm_dump_vmcb(const char *from, struct vmcb_struct *vmcb);
-extern void svm_stts(struct vcpu *v);
extern void svm_do_launch(struct vcpu *v);
-extern void svm_do_resume(struct vcpu *v);
-extern void svm_set_guest_time(struct vcpu *v, u64 gtime);
extern void arch_svm_do_resume(struct vcpu *v);
-extern int load_vmcb(struct arch_svm_struct *arch_svm, u64 phys_hsa);
-/* For debugging. Remove when no longer needed. */
-extern void svm_dump_host_regs(const char *from);
-
-extern void svm_migrate_timers(struct vcpu *v);
-
-/* ASID API */
-enum {
- ASID_AVAILABLE = 0,
- ASID_INUSE,
- ASID_RETIRED
-};
-#define INITIAL_ASID 0
-#define ASID_MAX 64
-
-struct asid_pool {
- spinlock_t asid_lock;
- u32 asid[ASID_MAX];
-};
-struct svm_percore_globals {
- void *hsa;
- u64 hsa_pa;
- void *scratch_hsa;
- u64 scratch_hsa_pa;
- struct asid_pool ASIDpool;
-};
+extern u64 root_vmcb_pa[NR_CPUS];
#define SVM_REG_EAX (0)
#define SVM_REG_ECX (1)
struct arch_svm_struct {
struct vmcb_struct *vmcb;
- void *host_save_area;
- u64 host_save_pa;
u64 vmcb_pa;
u32 *iopm;
u32 *msrpm;
struct timer hlt_timer; /* hlt ins emulation wakeup timer */
};
-struct vmcb_struct *alloc_vmcb(void);
-struct host_save_area *alloc_host_save_area(void);
-void free_vmcb(struct vmcb_struct *vmcb);
-void free_host_save_area(struct host_save_area *hsa);
-void dump_vmcb(void);
-int construct_vmcb(struct arch_svm_struct *, struct cpu_user_regs *);
+extern struct vmcb_struct *alloc_vmcb(void);
+extern struct host_save_area *alloc_host_save_area(void);
+extern void free_vmcb(struct vmcb_struct *vmcb);
+extern void free_host_save_area(struct host_save_area *hsa);
+
+extern int construct_vmcb(struct arch_svm_struct *, struct cpu_user_regs *);
+extern void destroy_vmcb(struct arch_svm_struct *);
+
+extern void setup_vmcb_dump(void);
#define VMCB_USE_HOST_ENV 1
#define VMCB_USE_SEPARATE_ENV 0
extern int start_vmx(void);
extern void vmcs_dump_vcpu(void);
extern void vmx_init_vmcs_config(void);
+extern void setup_vmcs_dump(void);
enum {
VMX_CPU_STATE_PAE_ENABLED=0,
return rc;
}
-/* Make sure that xen intercepts any FP accesses from current */
-static inline void vmx_stts(void)
-{
- unsigned long cr0;
- struct vcpu *v = current;
-
- /* FPU state already dirty? Then no need to setup_fpu() lazily. */
- if ( test_bit(_VCPUF_fpu_dirtied, &v->vcpu_flags) )
- return;
-
- /*
- * If the guest does not have TS enabled then we must cause and handle an
- * exception on first use of the FPU. If the guest *does* have TS enabled
- * then this is not necessary: no FPU activity can occur until the guest
- * clears CR0.TS, and we will initialise the FPU when that happens.
- */
- __vmread_vcpu(v, CR0_READ_SHADOW, &cr0);
- if ( !(cr0 & X86_CR0_TS) )
- {
- __vmread_vcpu(v, GUEST_CR0, &cr0);
- __vmwrite(GUEST_CR0, cr0 | X86_CR0_TS);
- __vm_set_bit(EXCEPTION_BITMAP, EXCEPTION_BITMAP_NM);
- }
-}
-
/* Works only for vcpu == current */
static inline int vmx_paging_enabled(struct vcpu *v)
{
}
-#define read_cr0() ({ \
- unsigned long __dummy; \
- __asm__( \
- "mov %%cr0,%0\n\t" \
- :"=r" (__dummy)); \
- __dummy; \
-})
-
-#define write_cr0(x) \
- __asm__("mov %0,%%cr0": :"r" ((unsigned long)x));
-
-#define read_cr4() ({ \
- unsigned long __dummy; \
- __asm__( \
- "mov %%cr4,%0\n\t" \
- :"=r" (__dummy)); \
- __dummy; \
-})
-
-#define write_cr4(x) \
- __asm__("mov %0,%%cr4": :"r" ((unsigned long)x));
+
+static inline unsigned long read_cr0(void)
+{
+ unsigned long __cr0;
+ __asm__("mov %%cr0,%0\n\t" :"=r" (__cr0));
+ return __cr0;
+}
+
+static inline void write_cr0(unsigned long val)
+{
+ __asm__("mov %0,%%cr0": :"r" ((unsigned long)val));
+}
+
+static inline unsigned long read_cr4(void)
+{
+ unsigned long __cr4;
+ __asm__("mov %%cr4,%0\n\t" :"=r" (__cr4));
+ return __cr4;
+}
+
+static inline void write_cr4(unsigned long val)
+{
+ __asm__("mov %0,%%cr4": :"r" ((unsigned long)val));
+}
+
+
+/* Clear and set 'TS' bit respectively */
+static inline void clts(void)
+{
+ __asm__ __volatile__ ("clts");
+}
+
+static inline void stts(void)
+{
+ write_cr0(X86_CR0_TS|read_cr0());
+}
+
/*
* Save the cr4 feature set we're using (ie
__sel; \
})
-/* Clear and set 'TS' bit respectively */
-#define clts() __asm__ __volatile__ ("clts")
-#define stts() write_cr0(X86_CR0_TS|read_cr0())
-
#define wbinvd() \
__asm__ __volatile__ ("wbinvd": : :"memory");
projects / xen.git / commitdiff